Projects

  
  • On Package I/O Interface Design for Xeon Phi
    Intel Corporation (June'11-present)

    My current job profile at Intel enables me to design Front End for OPIO (On Package I/O Interface) Design team for Xeon Phi. During this earlier phases, I had designed the Receiver Block including capacitively coupled, bias block, amplifier and offset cancellation. Following this, I guided the extensive layout review and solved many critical design challenges. Furthermore, I designed the Resistor Compensation block involving Comparator design, Tx, vref Ladder and also, worked on the clock distribution in Rx/Tx clusters, Sideband Rx & Local Clock Macros. Along with, leveraging scripting languages (Perl,Tcl) in evaluating circuits for corner cases and variations, I led the OPIO team during post-silicon debug for A0-Silicon in extensive debug tests and BIOS modelling

  • Dilligrocery.com, Founder, Developer

    Developed & designed inventory based grocery e-commerce serving individuals & corporates across Delhi, India by leveraging Prestashop framework

  • Design of 5-Bit Time-Interleaved Flash ADC
    EE315B, EE Dept., Stanford University.

    As part of the course, designed ADC which could operate at 400MS/s and could sample up to 1.6GHz signal. Furthermore employed Clocked Bootstrap Switch and Double Tail Latch Type Sense Amplifier based Comparator in the design

  • Comparative Study of Trans-impedance Amplifier Design
    Mentor: Prof. Borris Murmann, EE Dept., Stanford University.

    Analyzed trade-offs for various topologies specifically Capacitive feedback, Resistive feedback and Integrator-Differentiator approach For MEMS Resonators for GSM Systems.

  • Design of 3.5 GHz Wideband Trans impedance Amplifier
    EE214, EE Dept., Stanford University.

    Implemented Cherry Hooper Architecture for High Gain & Bandwidth in high speed Optical Communication Systems using 180nm CMOS Technology

  • Analysis and Design of High Frequency Transceiver LNA-Mixer
    EE314, EE Dept., Stanford University.

    Designed transceiver for WiFi Chipsets at operating frequency of 2.45GHz & Bandwidth of 200MHz with Power Gain 30dB and IIP3 ~ - 20dBm using 90nm CMOS Technology and Architecture of Inductively Degenerated Cascoded LNA & Double Balanced Active Mixer

  • VLSI Implementation of DNA Sequencing
    EE272, EE Dept., Stanford University.

    Employed low power Verilog coding techniques with hardware reusage and parallelism in designing hardware version of DNA Watersmith Algorithm; Later synthesized, placed and routed the complete ASIC design using 90nm CMOS Technology

  • "The Analysis and Design of Low Power Ring Oscillators with Frequency ~10-100 kHz": Summer Internship (May'08-July'08)
    Mentors: Prof. David Blaauw and Prof. Dennis Sylvester, EECS Dept., University Of Michigan.

    The project was based on "The Analysis and Design of Low Power Ring Oscillators with Frequency ~10-100 kHz".This project has been aimed at designing a clock with low power, low frequency, and low operating voltage using ring oscillator topology. It aims at determining the best possible configuration for the ring oscillators having the least power consumption and precise delay with lesser sensitivity to the variations in the temperature and supply voltage for frequencies of few kHz. The oscillator configurations have been designed at frequencies of 10 kHz and 100 kHz for an IBM 0.13μm and ST 65nm CMOS processes each. Click here for report in pdf format.

     

  • "Hardware Improvements for Rasterizer Design": Course Project
    Mentor: Prof. Mark Horowitz, EE Dept., Stanford University.

    The goal of the project is to get a render speed of 500 Million Polys/sec while consuming as little power and area as possible. The baseline rasterizer provided runs with a clock period of 1.05 ns and has a throughput of 0.083 Hence, our design meets the throughput requirements, has an optimized FOM value and also has power and area dissipation within the specified budget of 300mW and 1mm2 respectively. Our implementation strategy has received the "Lowest Energy Design with Minimum Area Overhead" award within the complete class and have given special presentation over the strategies being followed by us. (NOTE: Video Link for the presentation will be soon uploaded). Click here for report in pdf format. (Newly Added)

     

  • "Amplifier Design for Pore Based Bio-Sensor Chip": Course Design Project
    Mentor: Prof. Robert Dutton , EE Dept., Stanford University.

    The project is based on Designing the amplifier for pore based Bio-Sensor chip with the required specifications (as mentioned in design problem statement). The robust design for the amplifier circuit has been implemented and simulated in the HSPICE. Our design has received the "Best Robust Design with Least Power Consumption" award within the complete class. Click here for report in pdf format. (Newly Added)

     

  • "Networked RFID System (NRS) for Remote Services": B.Tech Project
    Mentor: Prof. S. Qureshi, EE Dept., IIT Kanpur.

    The project is based on Designing " Networked RFID System (NRS) " ,which is the extension of the project "Remote Gas Service" which has filed the National paten on April'08. The project is aimed at Designing a networked RFID system which integrates RFID reader & Web interface with the Web based Centralized Database Management System. The system has been extended and has been integrated with the wireless access using GSM modules & also using wired telephone lines to form Interactive voice response system to access Database. The project has been aimed with the objective of implementation in remote and rural areas to provide emergency services through efficient reliable system. The project is soon to be implemented within the campus for initial phase testing. Click here for presentation. Click here for report in pdf format. (Newly Added)

     

  • Analysis of High Speed Low Power Flip Flops
  • Mentor: Prof. S. Qureshi, EE Dept., IIT Kanpur.

The project is based on designing the compensation circuit for the CMOS thyristor based Current Starved Ring Oscillator design operating at 100kHz to reduce the Temperature Sensitivity of the circuit. Project is based on the analysis of the performance of different high speed low power flip flops such as Hybrid Latch Flip Flop, Sense Amplifier based Flip Flop, Semi- Dynamic Flip Flop, Master Slave Flip Flop, Clock Gated Master Slave Flip Flop and other modified designs of Sense Amplifier based Flip Flops. Report is under Construction

 

 

 
 
 

" When life throws lemons at you, you make a lemonade out of it " —Anonymous

" My greatest reward is my work " —Sherlock Holmes.